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Conference Day
October 23^rd

Tutorial
October 24^th

Location : AMD (2485 Augustine Dr, Santa Clara, CA 95054)

AGENDA
9:00 - 9:50 On site Registration (coffee provided)
9:50 - 10:00 Welcomes and introductions
10:00 - 10:40 Keynote Address
Allen Rush (AMD)

(Senior Fellow and Chief Architect for imaging, Machine Learning, and Computer Vision)

Session 1
10:40 - 11:20 - Presentation 1 - Yutian Huan (AMD)
         Title - DFT Verification of Bistable Arrays
11:20 - 12:00 - Presentation 2 - Tina Zhang (Samsung)
         Title - DFT Solutions for Time-To-Market
12:00 - 1:00 LUNCH - Free lunch

1:00 – 1:40 – Presentation 3 - Technology Spotlights
                  Mentor Graphics - 20 min
                  Synopsys - 20 min
Session 2
1:40 – 2:20 - Presentation 4 - Sreejit Chakravarty (Intel)
         Title - Infield Test for Automotive and Data Center
2:20 – 3:00 - Presentation 5 - Subhasish Mitra (Stanford)
         Title - QED and Symbolic QED: Dramatic Advances in Design Verification and System-Level Test

3:00 - 3:20 B R E A K
Session 3
3:20 - 4:00 - Presentation 6 - Stephen Crosher (MoorTec)
         Title - Trends in Internal Sensors for Test
4:00 - 4:40 - Presentation 7 - Gevorg Torjyan (Marvell)
         Title - DFT related RTL Enhancements
4:40 - 5:20 - Panel Discussion Referee: Jim Johnson
5:30 - 6:30 Happy Hour at TBD
Location : AMD (2485 Augustine Dr, Santa Clara, CA 95054)

Mixed Signal DFT : Trends, Principles, and Solutions

Teachers - Stephen Sunter

(Mentor, a Siemens Business)

Abstract: The tutorial will review trends in ad hoc analog DFT and fault simulation, then briefly consider the systematic DFT of IEEE 1149.1/4/6/7/8/10, and 1687. Next, it will describe essential principles of practical analog DFT (including BIST), such as addition, subtraction, and spec-based defect-oriented test, and how they are used in robust DFT techniques ranging from efficient analog defect simulation to over/under sampling methods that greatly improve range, resolution, and reusability. We’ll conclude with an overview of emerging standards IEEE P2427 and P1687.2 that facilitate these techniques for Analog Defect Coverage and Analog Test Access, respectively, and how they apply to the measurement of ISO 26262 metrics for automotive ICs.

9:30 - 10:00am On site Registration (coffee provided)

Introductions and Agenda

LUNCH - Free lunch

Q&A

3pm - Class ends

Conference Day October 23^rd	Tutorial October 24^th
Location : AMD (2485 Augustine Dr, Santa Clara, CA 95054) AGENDA 9:00 - 9:50 On site Registration (coffee provided) 9:50 - 10:00 Welcomes and introductions 10:00 - 10:40 Keynote Address Allen Rush (AMD) (Senior Fellow and Chief Architect for imaging, Machine Learning, and Computer Vision) Session 1 10:40 - 11:20 - Presentation 1 - Yutian Huan (AMD) Title - DFT Verification of Bistable Arrays 11:20 - 12:00 - Presentation 2 - Tina Zhang (Samsung) Title - DFT Solutions for Time-To-Market 12:00 - 1:00 LUNCH - Free lunch 1:00 – 1:40 – Presentation 3 - Technology Spotlights Mentor Graphics - 20 min Synopsys - 20 min Session 2 1:40 – 2:20 - Presentation 4 - Sreejit Chakravarty (Intel) Title - Infield Test for Automotive and Data Center 2:20 – 3:00 - Presentation 5 - Subhasish Mitra (Stanford) Title - QED and Symbolic QED: Dramatic Advances in Design Verification and System-Level Test 3:00 - 3:20 B R E A K Session 3 3:20 - 4:00 - Presentation 6 - Stephen Crosher (MoorTec) Title - Trends in Internal Sensors for Test 4:00 - 4:40 - Presentation 7 - Gevorg Torjyan (Marvell) Title - DFT related RTL Enhancements 4:40 - 5:20 - Panel Discussion Referee: Jim Johnson 5:30 - 6:30 Happy Hour at TBD	Location : AMD (2485 Augustine Dr, Santa Clara, CA 95054) Mixed Signal DFT : Trends, Principles, and Solutions Teachers - Stephen Sunter (Mentor, a Siemens Business) Abstract: The tutorial will review trends in ad hoc analog DFT and fault simulation, then briefly consider the systematic DFT of IEEE 1149.1/4/6/7/8/10, and 1687. Next, it will describe essential principles of practical analog DFT (including BIST), such as addition, subtraction, and spec-based defect-oriented test, and how they are used in robust DFT techniques ranging from efficient analog defect simulation to over/under sampling methods that greatly improve range, resolution, and reusability. We’ll conclude with an overview of emerging standards IEEE P2427 and P1687.2 that facilitate these techniques for Analog Defect Coverage and Analog Test Access, respectively, and how they apply to the measurement of ISO 26262 metrics for automotive ICs. 9:30 - 10:00am On site Registration (coffee provided) Introductions and Agenda LUNCH - Free lunch Q&A 3pm - Class ends