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Conference Day
November 11^th

Tutorial
November 12^th

Location : Crowne Plaza (Silicon Valley)

AGENDA
8:00 - 8:30 On site Registration (coffee provided)
8:30 - 8:40 Welcomes and introductions
8:40 - 9:10 Key Note Address

Eric Volkerink
(Chief Business officer and Executive VP of Heptagon)

(Click on Eric's picture for Bio)

Session 1
9:10 - 9:50 - Presentation 1 - Grady Giles (AMD)
                  Title - Optimizing Scan bandwidth to reduce TT
9:50 - 10:30 - Presentation 2 - Jennifer Dworak (SMU)
                  Title - Security Issues on ICs
10:30 - 11:00   B R E A K
11:00 – 12:15 – Presentation 3 - Technology Spotlights
                  Optimal Plus - 20 min
                  Mentor Graphics - 20 min
                  SiliconAid - 20 min

12:15 - 1:35 LUNCH - Free lunch

Session 2
1:35 – 2:10 - Presentation 4 - Neils Poulsen (Advantest)
                  Title - Test Challenges as a result of IoT
2:10 – 2:50 - Presentation 5 - Al Crouch (SiliconAid)
                  Title - IJTAG (1687 and 1149.1-2013)
2:50 - 3:30 B R E A K
Session 3
3:30 - 4:10 - Presentation 6 - Rob Aitken (ARM)
                  Title - Something Very Interesting
4:10 – 4:50 - Presentation 7 - Zoe Conroy (Cisco)
               Title - Bridging the Gap - Structural to Functional Test

4:50 - 6:00 - Panel Discussion Referee: Jim Johnson
4:50 - 6:00 Happy Hour during Panel

Location : AMD (1 AMD Pl, Sunnyvale, CA)

Design For Test (DFT) 101
Teachers – Alfred Crouch & Jim Johnson

Description : Introduction to the concepts of Design-For-Test and its justification and trade-offs. The day starts with basics of DFT covering the classic fault models (stuck-at, bridging and propagation delay) and their relevance to modern-day silicon defects. Most of the day is devoted to the DFT technique of internal scan, Memory BIST, Logic BIST and Compression, and some of the most used DFT related IEEE Standards: The day concludes with a review of some practical DFT guidelines.

9:00 - 9:30am On site Registration (coffee provided)

Introductions and Agenda

LUNCH - Free lunch sponsored by SiliconAid

~4pm - Class ends

Conference Day November 11^th	Tutorial November 12^th
Location : Crowne Plaza (Silicon Valley) AGENDA 8:00 - 8:30 On site Registration (coffee provided) 8:30 - 8:40 Welcomes and introductions 8:40 - 9:10 Key Note Address Eric Volkerink (Chief Business officer and Executive VP of Heptagon) (Click on Eric's picture for Bio) Session 1 9:10 - 9:50 - Presentation 1 - Grady Giles (AMD) Title - Optimizing Scan bandwidth to reduce TT 9:50 - 10:30 - Presentation 2 - Jennifer Dworak (SMU) Title - Security Issues on ICs 10:30 - 11:00 B R E A K 11:00 – 12:15 – Presentation 3 - Technology Spotlights Optimal Plus - 20 min Mentor Graphics - 20 min SiliconAid - 20 min 12:15 - 1:35 LUNCH - Free lunch Session 2 1:35 – 2:10 - Presentation 4 - Neils Poulsen (Advantest) Title - Test Challenges as a result of IoT 2:10 – 2:50 - Presentation 5 - Al Crouch (SiliconAid) Title - IJTAG (1687 and 1149.1-2013) 2:50 - 3:30 B R E A K Session 3 3:30 - 4:10 - Presentation 6 - Rob Aitken (ARM) Title - Something Very Interesting 4:10 – 4:50 - Presentation 7 - Zoe Conroy (Cisco) Title - Bridging the Gap - Structural to Functional Test 4:50 - 6:00 - Panel Discussion Referee: Jim Johnson 4:50 - 6:00 Happy Hour during Panel	Location : AMD (1 AMD Pl, Sunnyvale, CA) Design For Test (DFT) 101 Teachers – Alfred Crouch & Jim Johnson Description : Introduction to the concepts of Design-For-Test and its justification and trade-offs. The day starts with basics of DFT covering the classic fault models (stuck-at, bridging and propagation delay) and their relevance to modern-day silicon defects. Most of the day is devoted to the DFT technique of internal scan, Memory BIST, Logic BIST and Compression, and some of the most used DFT related IEEE Standards: The day concludes with a review of some practical DFT guidelines. 9:00 - 9:30am On site Registration (coffee provided) Introductions and Agenda LUNCH - Free lunch sponsored by SiliconAid ~4pm - Class ends